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carrysave-array-mult
- Carry save array multiplier design in verilog HDL
高速图像压缩编码器的VLSI结构设计研究
- 高速图像压缩编码器的VLSI结构设计研究.kdh 相当有水平的博士论文。里面详细讲到了如何设计小波变换VLSI结构。并对verilog hdl设计结构进行了评估-The high-speed image compression VLSI architecture design of the encoder the study. Kdh quite the level of Ph.D. thesis. Which talked about in detail how to design VLSI
verilogHDL
- 夏雨闻经典Verilog HDL详介绍了verilog HDL语法规范和无数经典例程，是和初学者学习，简单易懂。-Xia Yu Wen the classic Verilog HDL detailed introduction verilog HDL syntax specification and countless classic routines, and for beginners to learn, easy to understand.
High-speed-Digital-Design
- 高速数字设计，针对verilog HDL，中文版-High-speed digital design verilog HDL, the Chinese version
fpga-draw
- 二维图形加速器设计与实现。采用Verilog HDL语言对各功能模块进行了设计,包括画线、画圆、画椭圆、多边形填充以及区域复制等,总结了一套将算法使用硬件描述语言实现的一般流程.这是本人花了50大洋买的，吐血奉献-Design and implementation of a two-dimensional graphics accelerator. Using Verilog HDL language of each functional module design, draw lines, d
fpga
- 这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run
Verilogpinlvji
- 基于verilog HDL的频率计设计，多个模块，误差较小。-Based on the the verilog HDL frequency meter design, multiple modules, the error is smaller.
Motor.asm
- 基于verilog HDL步进电机驱动程序-The verilog HDL stepper motor driver
HDB3编解码器课程设计
- 对HDB3码型基本原理和特性的认识、对Quartus Ⅱ软件的熟练操作、对Verilog HDL的掌握和应用，这些知识都是进行电子设计的基本知识和能力，只有基础知识和能力扎实了，才能更好的进行更高层次的电子设计，所以这个设计也是对电子设计基本能力的很好的锻练。
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
jiaozhi
- 完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。 -Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an
rmii
- rmii 以太网接口时序源代码，值得开发借鉴的哦-verilog hdl
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
crc32
- crc-32 主要用于网络传输中的 检测，防止错误数据传输-verilog hdl
MOTOROLA-Verilog-HDL-Coding-standard
- 文档是关于verilogHDL的代码规范的，编写方是MOTOROLA，对于规范VerilogHDL格式有借鉴意义-Document is about verilogHDL code specification, the preparation side is MOTOROLA, VerilogHDL format for standardizing reference
shixunlaozhong
- 基于Verilog HDL语言的多功能数字钟，能够实现置位和清零功能。 -Verilog HDL language-based multi-function digital clock, to achieve set and clear functions.
src
- Concatenator for calculator synthesizable in verilog hdl.-Concatenator for calculator synthesizable in verilog hdl.
rs_code
- 本文在介绍卷积码原理和描述方式的基础上以1/2卷积码为例重点详细阐述了基于Verilog HDL 的卷积码的编器的设计-This paper introduced the convolution code on the principles and methods described in 1/2 convolutional code as an example focuses elaborated convolution based on Verilog HDL code compiled
hdl-manual
- Its a manual which consists of many vhdl programmes for beginners willing to learn VHDL and Verilog
Verilog_HDL
- 本文档记录了有关Verilog HDL语言学习的注意地方,以及一些关键语法的摘抄,初学者可以查找有关Verilog HDL的语法,加快学习。-This document records the Verilog HDL language learning about local attention, as well as some of the key excerpt syntax, beginners can find information about the syntax of Verilo